%0 Patent
%T Digital phase-locked loop with wide capture range, low phase noise, and reduced spurs
%U https://patents.google.com/patent/US8686771B2/
%G en
%A Frantzeskakis, Emmanouil
%A Syllaios, Ioannis L.
%A Sfikas, Georgios
%A Jensen, Henrik
%A Wu, Stephen
%A Sen, Padmanava
%D 2014-04-01
%K dpll
frequency
output signal
phase error
signal